一个4Mb 0.18 /spl mu/m 1T1MTJ切换MRAM内存

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332585

J. Nahas, T. Andre, Chitra K. Subramanian, B. Garni, H. Lin, A. Omair, W. Martino

{"title":"一个4Mb 0.18 /spl mu/m 1T1MTJ切换MRAM内存","authors":"J. Nahas, T. Andre, Chitra K. Subramanian, B. Garni, H. Lin, A. Omair, W. Martino","doi":"10.1109/ISSCC.2004.1332585","DOIUrl":null,"url":null,"abstract":"The 4.5/spl times/6.3mm/sup 2/ 25ns cycle-time 4Mb Toggle MRAM memory, built in 0.18 /spl mu/m 5M CMOS technology, uses a 1.55 /spl mu/m/sup 2/ bit cell with a single toggling magneto tunnel junction. The memory uses uni-directional programming currents with isolated write and read paths and balanced current mirror sense amplifier.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"A 4Mb 0.18 /spl mu/m 1T1MTJ Toggle MRAM memory\",\"authors\":\"J. Nahas, T. Andre, Chitra K. Subramanian, B. Garni, H. Lin, A. Omair, W. Martino\",\"doi\":\"10.1109/ISSCC.2004.1332585\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The 4.5/spl times/6.3mm/sup 2/ 25ns cycle-time 4Mb Toggle MRAM memory, built in 0.18 /spl mu/m 5M CMOS technology, uses a 1.55 /spl mu/m/sup 2/ bit cell with a single toggling magneto tunnel junction. The memory uses uni-directional programming currents with isolated write and read paths and balanced current mirror sense amplifier.\",\"PeriodicalId\":273317,\"journal\":{\"name\":\"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-09-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2004.1332585\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2004.1332585","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 10

摘要

4.5/spl次/6.3mm/sup 2/ 25ns周期时间4Mb切换MRAM内存，内置0.18 /spl μ m 5M CMOS技术，使用1.55 /spl μ m/sup 2/ bit单元和单个切换磁隧道结。存储器采用单向编程电流，具有隔离的读写路径和平衡电流镜像感测放大器。

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A 4Mb 0.18 /spl mu/m 1T1MTJ Toggle MRAM memory

The 4.5/spl times/6.3mm/sup 2/ 25ns cycle-time 4Mb Toggle MRAM memory, built in 0.18 /spl mu/m 5M CMOS technology, uses a 1.55 /spl mu/m/sup 2/ bit cell with a single toggling magneto tunnel junction. The memory uses uni-directional programming currents with isolated write and read paths and balanced current mirror sense amplifier.

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2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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