A design of 10-bit 25-MS/s SAR ADC using separated clock frequencies with high speed comparator in 180nm CMOS

A design of a 10-bit 25 MS/s Successive Approximation Register (SAR) Analog to Digital Converter (ADC) that uses improved dynamic comparator has been introduced in this paper. In this improved dynamic comparator, a novel pre-amplifier is proposed in order to enhance the bandwidth up to 817 MHz when compared to classical pre-amplifier structures. Besides, a modified dynamic latch with driving simultaneously gate and bulk terminals are also presented in this work. The whole of SAR ADC is designed and simulated in 180nm CMOS process with the structure based on the conventional architecture but reduced the capacitor array mismatch by using separated clock frequencies to control simultaneously comparator and SAR combination logic. Thus, this design works with the clock frequency of 0.5 GHz achieving a maximum sampling rate at 25 MS/s and 1.8V supply voltage. Without calibration technique, sampling at 25 MS/s, peak DNL and peak INL of original ADCs averaged across the array are 0.7 least significant bit (LSB) and 3.6 LSB, respectively.