Micro-21 from the program chair

The instruction queue is a critical component of the proposed mlcroarchitecture where executable instructions are detected and delivered to the execution unit. This paper clarifies the issue of loading instructions into the instruction queue and evaluates the resulting performance due to different schemes. paths are identified in the complicated UNIX programs so that trace scheduling can be effectively applied. Experimental results are provided for ten UNIX system and CAD programs which all exhibit complicated control structure. This is the first paper to address the issue of applying trace scheduling to complicated programs. The work is critical to adapting trace scheduling to RISC's and other upcoming pipelined, parallel mlcroarchltectures. Research The CMOS 370 has some Control Store on chip and some off. A small on-chip Control Store holds the first two microwords of each microsequence (target of conditional branches). A close look reveals that the two-level Control Store structure can be viewed as a programmer managed target instruction buffer. This structure makes it possible to access one microinstruction from a (mostly off-chip) large Control store every cycle while achieving a short cycle time. Efficient trapping is proposed to support efficient instruction emulation in processors with hardwired control. This makes the issue of instruction set design relatively independent of the implementation (hardwired or microprogrammed). • "Multiple Instruction Issue and Single-Chip Processors," A. Pleszkun and G. Sohi, U. of Wisconsin-Madison. Sometimes issuing multiple instructions is not a win. It would be interesting to experiment on the effect of compilation support (trace scheduling, register allocation, etc.) on the instruction issue rate. Comparing the results presented in this paper and those presented by the VLIW team, compilation support seems to be critical for issuing multiple instructions per cycle. The paper discusses the dilemma due to the interdependence between data routing and code scheduling in ASIC code generation. This issue corresponds closely to the one regarding the code scheduling and register allocation for pipelined and/or wide instruction architectures. The trend is to consider both factors together during code generation. The dynamic reconfigurability is a very interesting feature of the proposed ASIC paradigm. However, the slow prototype makes one wonder if a simple microprocessor can be programmed to achieve the same performance for the target applications. • "Implementing a Prolog Machine with Multiple Functional Units," A. Singhal and Y. Patt, U. C. Berkeley. Parallel unification and execution result in factor of 4 speedup over the Berkeley PLM. …