{"title":"利用多层并行性的大粒度数据流架构","authors":"E. Zehendner, T. Ungerer","doi":"10.1109/CMPEUR.1992.218492","DOIUrl":null,"url":null,"abstract":"A data flow architecture is presented that utilizes several levels of parallelism by a three-level hierarchical hardware structure. Task level parallelism was exploited by the architectural structure of a distributed memory multiprocessor and a load distribution strategy that supports parallel execution of procedure activations. Block and instruction level parallelism was utilized by token-passing, similar to large-grain data flow. Subinstruction level parallelism was exploited by single instruction, multiple data (SIMD) evaluation of complex machine instructions.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A large-grain data flow architecture utilizing multiple levels of parallelism\",\"authors\":\"E. Zehendner, T. Ungerer\",\"doi\":\"10.1109/CMPEUR.1992.218492\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A data flow architecture is presented that utilizes several levels of parallelism by a three-level hierarchical hardware structure. Task level parallelism was exploited by the architectural structure of a distributed memory multiprocessor and a load distribution strategy that supports parallel execution of procedure activations. Block and instruction level parallelism was utilized by token-passing, similar to large-grain data flow. Subinstruction level parallelism was exploited by single instruction, multiple data (SIMD) evaluation of complex machine instructions.<<ETX>>\",\"PeriodicalId\":390273,\"journal\":{\"name\":\"CompEuro 1992 Proceedings Computer Systems and Software Engineering\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-05-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"CompEuro 1992 Proceedings Computer Systems and Software Engineering\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CMPEUR.1992.218492\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CMPEUR.1992.218492","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A large-grain data flow architecture utilizing multiple levels of parallelism
A data flow architecture is presented that utilizes several levels of parallelism by a three-level hierarchical hardware structure. Task level parallelism was exploited by the architectural structure of a distributed memory multiprocessor and a load distribution strategy that supports parallel execution of procedure activations. Block and instruction level parallelism was utilized by token-passing, similar to large-grain data flow. Subinstruction level parallelism was exploited by single instruction, multiple data (SIMD) evaluation of complex machine instructions.<>
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