{"title":"扩展状态码的摩尔有限状态机设计","authors":"L. Titarenko, O. Hebda, A. Barkalov","doi":"10.2498/iti.2013.0504","DOIUrl":null,"url":null,"abstract":"The new method is proposed for reduction of chip area occupied by logic circuit of Moore FSM implemented with PLAs. It is based on the representation of the state code as a concatenation of the code of class of pseudoequivalent states and code of state inside this class. Such an approach allows elimination of dependence among states and output variables. It allows the hardware reduction in the FSM logic circuit in comparison with known design methods.","PeriodicalId":262789,"journal":{"name":"Proceedings of the ITI 2013 35th International Conference on Information Technology Interfaces","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design of moore finite state machine with extended state codes\",\"authors\":\"L. Titarenko, O. Hebda, A. Barkalov\",\"doi\":\"10.2498/iti.2013.0504\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The new method is proposed for reduction of chip area occupied by logic circuit of Moore FSM implemented with PLAs. It is based on the representation of the state code as a concatenation of the code of class of pseudoequivalent states and code of state inside this class. Such an approach allows elimination of dependence among states and output variables. It allows the hardware reduction in the FSM logic circuit in comparison with known design methods.\",\"PeriodicalId\":262789,\"journal\":{\"name\":\"Proceedings of the ITI 2013 35th International Conference on Information Technology Interfaces\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-10-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the ITI 2013 35th International Conference on Information Technology Interfaces\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.2498/iti.2013.0504\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the ITI 2013 35th International Conference on Information Technology Interfaces","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.2498/iti.2013.0504","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of moore finite state machine with extended state codes
The new method is proposed for reduction of chip area occupied by logic circuit of Moore FSM implemented with PLAs. It is based on the representation of the state code as a concatenation of the code of class of pseudoequivalent states and code of state inside this class. Such an approach allows elimination of dependence among states and output variables. It allows the hardware reduction in the FSM logic circuit in comparison with known design methods.