3gbps, 5000 ppm扩频SerDes PHY与频率跟踪相位插补器串行ATA

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI:10.1109/VLSIC.2003.1221175

Morishige Aoyama, Kazuo Ogasawara, Mitsutoshi Sugawara, Terukazu Ishibashi, Takashi Ishibashi, S. Shimoyama, Kouichi Yamaguchi, Tomonori Yanagita, Toshihiro Noma

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引用次数: 42

摘要

我们开发了一个5000 ppm的扩频序列化/反序列化(SerDes)物理层(PHY)芯片，符合串行AT附件(ATA)。该芯片采用0.15 /spl mu/m 1.5 V CMOS工艺制造，包括一个自运行扩频载波发生器，提供发射和接收块，一个自运行相位插补器，恢复+/-5000 ppm扩频接收(RX)时钟和数据。

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3 Gbps, 5000 ppm spread spectrum SerDes PHY with frequency tracking phase interpolator for serial ATA

We have developed a 5000 ppm spread spectrum Serializer/Deserializer (SerDes) physical layer (PHY) chip compliant with Serial AT Attachment (ATA). The chip was fabricated with a 0.15 /spl mu/m 1.5 V CMOS process and includes a self-running spread spectrum carrier generator to provide both transmit and receive block, a self-running phase interpolator to recover the +/-5000 ppm spread spectrum receive (RX) clock and data.

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2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

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