CMOS/BiCMOS电路中I/sub DDQ/故障检测的故障表征和可测试性设计技术

Canadian Conference on Electrical and Computer Engineering 2001. Conference Proceedings (Cat. No.01TH8555) Pub Date : 2001-05-13 DOI:10.1109/CCECE.2001.933594

K. Raahemifar, Mokhtar Ahmadi

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引用次数: 0

摘要

本文提供了基于仿真的CMOS/BiCMOS逻辑族故障表征研究结果。我们发现大多数短路导致I/sub DDQ/故障，而开放缺陷导致延迟或卡开故障。我们提出了一种可测试性设计技术，用于检测CMOS/BiCMOS逻辑电路中的短路和桥接故障。研究了这种电路修改对正常模式下电路行为的影响。

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Fault characterizations and design-for-testability technique for detecting I/sub DDQ/ faults in CMOS/BiCMOS circuits

This paper provides the results of a simulation-based fault characterization study of CMOS/BiCMOS logic families. We show that most of the shorts cause I/sub DDQ/ faults, while open defects result in delay or stuck-open faults. We propose a design-for-testability technique for detecting short and bridging faults in CMOS/BiCMOS logic circuits. The impact of this circuit modification on the behavior of the circuit in normal mode is investigated.

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Canadian Conference on Electrical and Computer Engineering 2001. Conference Proceedings (Cat. No.01TH8555)

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