{"title":"二维离散小波变换的VLSI结构研究","authors":"K. Raj, Vedvrat","doi":"10.1109/ICPCES.2010.5698715","DOIUrl":null,"url":null,"abstract":"In this paper we presented the different VLSI architectures for the computation of 2-D Discrete Wavelet Transform (DWT). These Architectures are based on Recursive Pyramid Algorithm (RPA), Systolic Array architecture and Parallel Filter architecture. A comparative analysis, on the basis of computational complexity and hardware utilization, of these architectures is presented here.","PeriodicalId":439893,"journal":{"name":"2010 International Conference on Power, Control and Embedded Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A study of VLSI architectures for 2-D Discrete Wavelet Transform\",\"authors\":\"K. Raj, Vedvrat\",\"doi\":\"10.1109/ICPCES.2010.5698715\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we presented the different VLSI architectures for the computation of 2-D Discrete Wavelet Transform (DWT). These Architectures are based on Recursive Pyramid Algorithm (RPA), Systolic Array architecture and Parallel Filter architecture. A comparative analysis, on the basis of computational complexity and hardware utilization, of these architectures is presented here.\",\"PeriodicalId\":439893,\"journal\":{\"name\":\"2010 International Conference on Power, Control and Embedded Systems\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 International Conference on Power, Control and Embedded Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICPCES.2010.5698715\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International Conference on Power, Control and Embedded Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICPCES.2010.5698715","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A study of VLSI architectures for 2-D Discrete Wavelet Transform
In this paper we presented the different VLSI architectures for the computation of 2-D Discrete Wavelet Transform (DWT). These Architectures are based on Recursive Pyramid Algorithm (RPA), Systolic Array architecture and Parallel Filter architecture. A comparative analysis, on the basis of computational complexity and hardware utilization, of these architectures is presented here.
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