Design and Performance Analysis of Energy Efficient 11T SRAM (E2S11T) Cell for High Performance and Low Power Applications

The SRAM based cache memory has been radically increasing in low power applications. The on-chip data processing and computations have been consistently increasing for Wireless Sensor Networks (WSN) and Internet-of-Things (IoT) applications. This demands the constant improvement over the power, performance, stability, and energy efficiency. The challenges rely on power and performance of SRAM as the technology node reduces. In this paper, design of Energy Efficient SRAM (E2S11T) cell is proposed. The proposed cell contains 11-Transistors and implemented using 45 nm CMOS technology. The average dynamic power of the proposed cell is minimized by of 86.68%,86.77%,61.48% and 38.47% compared to C6T, S8T, LPHS10T and HSF11T cells, respectively. The write delay is reasonably improved about 32.58%, 34.36% and 8.43% against C6T, S8T and LPHS10T cells respectively. The read delay is also improved as well as stability have been improved due to three transistors. The proposed E2S11T cell is proven to be stable in worse conditions against temperature and works without any degradation as low as 500 mV. The cell is statistically analysed by performing Monte-Carlo (MC) simulation to validate the stability of the cell.