不同掺杂浓度下10nm和16nm多通道FinFET的设计与比较分析

Veera Venkata Sai Amudalapalli, Hima Bindu Valiveti, Asisa Kumar Panigrahy
{"title":"不同掺杂浓度下10nm和16nm多通道FinFET的设计与比较分析","authors":"Veera Venkata Sai Amudalapalli, Hima Bindu Valiveti, Asisa Kumar Panigrahy","doi":"10.1109/ICCES57224.2023.10192682","DOIUrl":null,"url":null,"abstract":"Nanotechnology chip designing focuses on the Nano-electronics concepts and produces circuits that are built with the components sizing in nanometers (nm). Smaller channel lengths in the range of nm not only increase the speed of operation but also help in accommodating more transistors in the chip and also decreases power consumption. One of the major side effects of miniaturizing of the transistors are leakages. The current work emphasizes on design of 16nm and 10nm Nanosheet FinFET (NS-FET) with Gate All Around (GAA) technology and fully depleted Silicon on Insulator (SoI). The design of multi-channel NS-FET with uniform doping concentration level varying form 1e16 cm-3 to 1e18 cm-3 for the two channels of the NS-FET is presented for both 16nm and 10nm channel lengths. The impact of GAA nm-technology NS-FinFET devices are thoroughly investigated using Visual technology computer-aided design (Visual TCAD) simulator for parameters like (VGS-ID), transfer characteristics, Ion/Ioff ratio and Drain Induced Barrier Lowering (DIBL). Comparative results for 16nm and 10nm technology are presented under varying doping concentrations and 10nm technology. The 10nm technology exhibits better transfer characteristics in terms of threshold voltage, current ratio and DIBL.","PeriodicalId":442189,"journal":{"name":"2023 8th International Conference on Communication and Electronics Systems (ICCES)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design and Comparative Analysis of 10nm and 16nm Multichannel Nanosheet FinFET with Varying Doping Concentrations\",\"authors\":\"Veera Venkata Sai Amudalapalli, Hima Bindu Valiveti, Asisa Kumar Panigrahy\",\"doi\":\"10.1109/ICCES57224.2023.10192682\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Nanotechnology chip designing focuses on the Nano-electronics concepts and produces circuits that are built with the components sizing in nanometers (nm). Smaller channel lengths in the range of nm not only increase the speed of operation but also help in accommodating more transistors in the chip and also decreases power consumption. One of the major side effects of miniaturizing of the transistors are leakages. The current work emphasizes on design of 16nm and 10nm Nanosheet FinFET (NS-FET) with Gate All Around (GAA) technology and fully depleted Silicon on Insulator (SoI). The design of multi-channel NS-FET with uniform doping concentration level varying form 1e16 cm-3 to 1e18 cm-3 for the two channels of the NS-FET is presented for both 16nm and 10nm channel lengths. The impact of GAA nm-technology NS-FinFET devices are thoroughly investigated using Visual technology computer-aided design (Visual TCAD) simulator for parameters like (VGS-ID), transfer characteristics, Ion/Ioff ratio and Drain Induced Barrier Lowering (DIBL). Comparative results for 16nm and 10nm technology are presented under varying doping concentrations and 10nm technology. The 10nm technology exhibits better transfer characteristics in terms of threshold voltage, current ratio and DIBL.\",\"PeriodicalId\":442189,\"journal\":{\"name\":\"2023 8th International Conference on Communication and Electronics Systems (ICCES)\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 8th International Conference on Communication and Electronics Systems (ICCES)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCES57224.2023.10192682\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 8th International Conference on Communication and Electronics Systems (ICCES)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCES57224.2023.10192682","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

纳米技术芯片设计的重点是纳米电子学概念,并生产出以纳米(nm)为尺寸的元件构建的电路。纳米范围内更小的通道长度不仅提高了操作速度,而且有助于在芯片中容纳更多的晶体管,还降低了功耗。晶体管小型化的主要副作用之一是漏电。目前的工作重点是采用栅极(GAA)技术和完全耗尽绝缘体上硅(SoI)技术设计16nm和10nm纳米片FinFET (NS-FET)。本文提出了一种多通道NS-FET的设计方法,其掺杂浓度水平为1e16 cm-3至1e18 cm-3,通道长度分别为16nm和10nm。利用Visual technology计算机辅助设计(Visual TCAD)模拟器对(VGS-ID)、传输特性、离子/开关比和漏极诱导势垒降低(DIBL)等参数的影响进行了深入研究。在不同掺杂浓度和10nm工艺下,比较了16nm和10nm工艺的结果。10nm技术在阈值电压、电流比和DIBL方面表现出更好的转移特性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design and Comparative Analysis of 10nm and 16nm Multichannel Nanosheet FinFET with Varying Doping Concentrations
Nanotechnology chip designing focuses on the Nano-electronics concepts and produces circuits that are built with the components sizing in nanometers (nm). Smaller channel lengths in the range of nm not only increase the speed of operation but also help in accommodating more transistors in the chip and also decreases power consumption. One of the major side effects of miniaturizing of the transistors are leakages. The current work emphasizes on design of 16nm and 10nm Nanosheet FinFET (NS-FET) with Gate All Around (GAA) technology and fully depleted Silicon on Insulator (SoI). The design of multi-channel NS-FET with uniform doping concentration level varying form 1e16 cm-3 to 1e18 cm-3 for the two channels of the NS-FET is presented for both 16nm and 10nm channel lengths. The impact of GAA nm-technology NS-FinFET devices are thoroughly investigated using Visual technology computer-aided design (Visual TCAD) simulator for parameters like (VGS-ID), transfer characteristics, Ion/Ioff ratio and Drain Induced Barrier Lowering (DIBL). Comparative results for 16nm and 10nm technology are presented under varying doping concentrations and 10nm technology. The 10nm technology exhibits better transfer characteristics in terms of threshold voltage, current ratio and DIBL.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信