Veera Venkata Sai Amudalapalli, Hima Bindu Valiveti, Asisa Kumar Panigrahy
{"title":"不同掺杂浓度下10nm和16nm多通道FinFET的设计与比较分析","authors":"Veera Venkata Sai Amudalapalli, Hima Bindu Valiveti, Asisa Kumar Panigrahy","doi":"10.1109/ICCES57224.2023.10192682","DOIUrl":null,"url":null,"abstract":"Nanotechnology chip designing focuses on the Nano-electronics concepts and produces circuits that are built with the components sizing in nanometers (nm). Smaller channel lengths in the range of nm not only increase the speed of operation but also help in accommodating more transistors in the chip and also decreases power consumption. One of the major side effects of miniaturizing of the transistors are leakages. The current work emphasizes on design of 16nm and 10nm Nanosheet FinFET (NS-FET) with Gate All Around (GAA) technology and fully depleted Silicon on Insulator (SoI). The design of multi-channel NS-FET with uniform doping concentration level varying form 1e16 cm-3 to 1e18 cm-3 for the two channels of the NS-FET is presented for both 16nm and 10nm channel lengths. The impact of GAA nm-technology NS-FinFET devices are thoroughly investigated using Visual technology computer-aided design (Visual TCAD) simulator for parameters like (VGS-ID), transfer characteristics, Ion/Ioff ratio and Drain Induced Barrier Lowering (DIBL). Comparative results for 16nm and 10nm technology are presented under varying doping concentrations and 10nm technology. The 10nm technology exhibits better transfer characteristics in terms of threshold voltage, current ratio and DIBL.","PeriodicalId":442189,"journal":{"name":"2023 8th International Conference on Communication and Electronics Systems (ICCES)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design and Comparative Analysis of 10nm and 16nm Multichannel Nanosheet FinFET with Varying Doping Concentrations\",\"authors\":\"Veera Venkata Sai Amudalapalli, Hima Bindu Valiveti, Asisa Kumar Panigrahy\",\"doi\":\"10.1109/ICCES57224.2023.10192682\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Nanotechnology chip designing focuses on the Nano-electronics concepts and produces circuits that are built with the components sizing in nanometers (nm). Smaller channel lengths in the range of nm not only increase the speed of operation but also help in accommodating more transistors in the chip and also decreases power consumption. One of the major side effects of miniaturizing of the transistors are leakages. The current work emphasizes on design of 16nm and 10nm Nanosheet FinFET (NS-FET) with Gate All Around (GAA) technology and fully depleted Silicon on Insulator (SoI). The design of multi-channel NS-FET with uniform doping concentration level varying form 1e16 cm-3 to 1e18 cm-3 for the two channels of the NS-FET is presented for both 16nm and 10nm channel lengths. The impact of GAA nm-technology NS-FinFET devices are thoroughly investigated using Visual technology computer-aided design (Visual TCAD) simulator for parameters like (VGS-ID), transfer characteristics, Ion/Ioff ratio and Drain Induced Barrier Lowering (DIBL). Comparative results for 16nm and 10nm technology are presented under varying doping concentrations and 10nm technology. The 10nm technology exhibits better transfer characteristics in terms of threshold voltage, current ratio and DIBL.\",\"PeriodicalId\":442189,\"journal\":{\"name\":\"2023 8th International Conference on Communication and Electronics Systems (ICCES)\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 8th International Conference on Communication and Electronics Systems (ICCES)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCES57224.2023.10192682\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 8th International Conference on Communication and Electronics Systems (ICCES)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCES57224.2023.10192682","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and Comparative Analysis of 10nm and 16nm Multichannel Nanosheet FinFET with Varying Doping Concentrations
Nanotechnology chip designing focuses on the Nano-electronics concepts and produces circuits that are built with the components sizing in nanometers (nm). Smaller channel lengths in the range of nm not only increase the speed of operation but also help in accommodating more transistors in the chip and also decreases power consumption. One of the major side effects of miniaturizing of the transistors are leakages. The current work emphasizes on design of 16nm and 10nm Nanosheet FinFET (NS-FET) with Gate All Around (GAA) technology and fully depleted Silicon on Insulator (SoI). The design of multi-channel NS-FET with uniform doping concentration level varying form 1e16 cm-3 to 1e18 cm-3 for the two channels of the NS-FET is presented for both 16nm and 10nm channel lengths. The impact of GAA nm-technology NS-FinFET devices are thoroughly investigated using Visual technology computer-aided design (Visual TCAD) simulator for parameters like (VGS-ID), transfer characteristics, Ion/Ioff ratio and Drain Induced Barrier Lowering (DIBL). Comparative results for 16nm and 10nm technology are presented under varying doping concentrations and 10nm technology. The 10nm technology exhibits better transfer characteristics in terms of threshold voltage, current ratio and DIBL.