低功耗，小芯片尺寸锁相环采用半数字存储，而不是大的环路滤波电容

2010 IEEE International Conference on Networked Embedded Systems for Enterprise Applications Pub Date : 2010-12-30 DOI:10.1109/NESEA.2010.5678055

M. Dietl, P. Sareen

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引用次数: 6

摘要

传统的低带宽锁相环使用一个外部电容和一个大的片上纹波电容。提出了一种新的锁相环结构，消除了外部电容的需要。此外，片上电容器的价值大大减少，减少了芯片尺寸。所提出的锁相环架构功耗非常低。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Low power, small die-size PLL using semi-digital storage instead of big loop filter capacitance

Conventional low bandwidth Phase lock loop uses an external Capacitor together with a big on chip ripple capacitor. A new architecture of a Phase lock loop is proposed which eliminates the need for an external capacitor. Also the value of the on chip capacitor is reduced drastically, reducing the chip size. The PLL architecture proposed uses very low power.

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2010 IEEE International Conference on Networked Embedded Systems for Enterprise Applications

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