Self-aligned planar technology for GaAs integrated circuits

This paper describes a technological process well adapted for making high speed GaAs FET integrated circuits. The main features of this technology are : • a completely planar structure obtained by using ion implantation. • a self-allgnment of transistor gates between source and drain contacts. The process described includes the self alignment feature of that developed in our laboratory for microwave submicron gate GaAs MESFET's (1). The dielectric layer needed to insulate the two levels of interconnections can have a detrimental effect on transistors characteristics. This has been avoided by using the proper materials and deposition conditions. The results for different materials will be compared and some figures of merit of NOR-gate circuits will be given.