{"title":"一种改进的7电平降阶开关对称逆变器","authors":"Kshirod Kumar Rout, S. Mishra","doi":"10.1109/NPEC.2018.8476780","DOIUrl":null,"url":null,"abstract":"Multi level inverters (MLI) are being preferred over conventional two level inverters as the former topologies have minimum harmonic distortion, electromagnetic interference and higher DC link voltages. On the other hand, these devices have some inherent drawbacks like increased number of switches, complicated control techniques and requirement of many voltage sources. A conventional topology uses 12 switches for a 7-level MLI design. In this paper, a modified reduced switch topology based 7-level inverter is proposed which require only 7 or 6 switches. Design, simulation and comparison of 7-level 7switch, and 7-level 6-switch inverters are carried out in MATLAB/SIMULINK environment. A hardware implementation of the above topologies for validation is also included.","PeriodicalId":170822,"journal":{"name":"2018 National Power Engineering Conference (NPEC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A Modified 7-Level Reduced Switch Symmetrical Inverter\",\"authors\":\"Kshirod Kumar Rout, S. Mishra\",\"doi\":\"10.1109/NPEC.2018.8476780\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Multi level inverters (MLI) are being preferred over conventional two level inverters as the former topologies have minimum harmonic distortion, electromagnetic interference and higher DC link voltages. On the other hand, these devices have some inherent drawbacks like increased number of switches, complicated control techniques and requirement of many voltage sources. A conventional topology uses 12 switches for a 7-level MLI design. In this paper, a modified reduced switch topology based 7-level inverter is proposed which require only 7 or 6 switches. Design, simulation and comparison of 7-level 7switch, and 7-level 6-switch inverters are carried out in MATLAB/SIMULINK environment. A hardware implementation of the above topologies for validation is also included.\",\"PeriodicalId\":170822,\"journal\":{\"name\":\"2018 National Power Engineering Conference (NPEC)\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 National Power Engineering Conference (NPEC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NPEC.2018.8476780\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 National Power Engineering Conference (NPEC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NPEC.2018.8476780","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Modified 7-Level Reduced Switch Symmetrical Inverter
Multi level inverters (MLI) are being preferred over conventional two level inverters as the former topologies have minimum harmonic distortion, electromagnetic interference and higher DC link voltages. On the other hand, these devices have some inherent drawbacks like increased number of switches, complicated control techniques and requirement of many voltage sources. A conventional topology uses 12 switches for a 7-level MLI design. In this paper, a modified reduced switch topology based 7-level inverter is proposed which require only 7 or 6 switches. Design, simulation and comparison of 7-level 7switch, and 7-level 6-switch inverters are carried out in MATLAB/SIMULINK environment. A hardware implementation of the above topologies for validation is also included.