Clock gating circuit design based on data-driven improvements

In order to decrease large the dynamic power consumption produced by the invalid flip-flop in integrated circuits, a new clock gating circuit has been designed based on data-driven clock gating technology in this paper. Firstly, the XOR gate in the flip-flop module is replaced with and or gate to control and reduce flip-flop activities. A data holding module was added to maintain the correctness of timing and prevent burrs. The designed circuit was simulated based on ISCAS89 benchmark circuit on ModelSim experiment platform. The simulation results indicates that the dynamic power consumption of the circuit can be reduced by more than 20%, showing that the new clock gating circuit is