Yuzhe Chen, Yubo Wang, Dejian Li, Changzheng Dong, Jie Gan, Jinlong Pan
{"title":"用于芯片间数据帧传输的帧封隔器设计","authors":"Yuzhe Chen, Yubo Wang, Dejian Li, Changzheng Dong, Jie Gan, Jinlong Pan","doi":"10.1109/IAEAC54830.2022.9929540","DOIUrl":null,"url":null,"abstract":"This paper introduces the design of a frame packer for the transmission of data frame protocol, which can be applied to the interaction of data between chips. Through the frame packer designed in this paper, the measurement value in chip A can be transformed into the format of data frame which can be in accordance with the transmission protocol, and the data transmission between chip A and chip B can be realized through SPI. The MCU chip with this frame packer design has passed verification by VCS and FPGA. The chip has been successfully taped out. The test results of the samples show that the function design of the frame packer is useful and the performance is good.","PeriodicalId":349113,"journal":{"name":"2022 IEEE 6th Advanced Information Technology, Electronic and Automation Control Conference (IAEAC )","volume":"244 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of A Frame Packer for Data FrameTransmission between Chips\",\"authors\":\"Yuzhe Chen, Yubo Wang, Dejian Li, Changzheng Dong, Jie Gan, Jinlong Pan\",\"doi\":\"10.1109/IAEAC54830.2022.9929540\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper introduces the design of a frame packer for the transmission of data frame protocol, which can be applied to the interaction of data between chips. Through the frame packer designed in this paper, the measurement value in chip A can be transformed into the format of data frame which can be in accordance with the transmission protocol, and the data transmission between chip A and chip B can be realized through SPI. The MCU chip with this frame packer design has passed verification by VCS and FPGA. The chip has been successfully taped out. The test results of the samples show that the function design of the frame packer is useful and the performance is good.\",\"PeriodicalId\":349113,\"journal\":{\"name\":\"2022 IEEE 6th Advanced Information Technology, Electronic and Automation Control Conference (IAEAC )\",\"volume\":\"244 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-10-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE 6th Advanced Information Technology, Electronic and Automation Control Conference (IAEAC )\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IAEAC54830.2022.9929540\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE 6th Advanced Information Technology, Electronic and Automation Control Conference (IAEAC )","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IAEAC54830.2022.9929540","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of A Frame Packer for Data FrameTransmission between Chips
This paper introduces the design of a frame packer for the transmission of data frame protocol, which can be applied to the interaction of data between chips. Through the frame packer designed in this paper, the measurement value in chip A can be transformed into the format of data frame which can be in accordance with the transmission protocol, and the data transmission between chip A and chip B can be realized through SPI. The MCU chip with this frame packer design has passed verification by VCS and FPGA. The chip has been successfully taped out. The test results of the samples show that the function design of the frame packer is useful and the performance is good.