{"title":"64点FFT在多处理器片上系统的实现","authors":"Roberto Airoldi, F. Garzia, J. Nurmi","doi":"10.1109/RME.2009.5201371","DOIUrl":null,"url":null,"abstract":"This paper describes the implementation of a 64-point FFT on a Multi-Processor System-on-Chip (MPSoC) composed of 9 homogeneous clusters. Each cluster is built around a RISC processor. The implementation technique adopted for the mapping of the FFT produces a speed-up of 6x which is close to the theoretical limit. This is due to a reduced overhead of intra-clusters communication.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"89 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Implementation of a 64-point FFT on a Multi-Processor System-on-Chip\",\"authors\":\"Roberto Airoldi, F. Garzia, J. Nurmi\",\"doi\":\"10.1109/RME.2009.5201371\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the implementation of a 64-point FFT on a Multi-Processor System-on-Chip (MPSoC) composed of 9 homogeneous clusters. Each cluster is built around a RISC processor. The implementation technique adopted for the mapping of the FFT produces a speed-up of 6x which is close to the theoretical limit. This is due to a reduced overhead of intra-clusters communication.\",\"PeriodicalId\":245992,\"journal\":{\"name\":\"2009 Ph.D. Research in Microelectronics and Electronics\",\"volume\":\"89 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-07-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 Ph.D. Research in Microelectronics and Electronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RME.2009.5201371\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 Ph.D. Research in Microelectronics and Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RME.2009.5201371","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Implementation of a 64-point FFT on a Multi-Processor System-on-Chip
This paper describes the implementation of a 64-point FFT on a Multi-Processor System-on-Chip (MPSoC) composed of 9 homogeneous clusters. Each cluster is built around a RISC processor. The implementation technique adopted for the mapping of the FFT produces a speed-up of 6x which is close to the theoretical limit. This is due to a reduced overhead of intra-clusters communication.