重掺杂N+缓冲层直接键合igbt的分析

8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings Pub Date : 1996-05-20 DOI:10.1109/ISPSD.1996.509511

S. Tu, G. Tam, P. Tam, H. Tsoi, A. Taomoto

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引用次数: 15

摘要

本文描述和分析了直接晶圆键合和注入N+缓冲层制备高速igbt的方法。在晶圆键合过程之前，可以通过改变N+植入剂量来控制导通状态电压降和关断下降时间之间的权衡。已经获得了开关时间小于100纳秒的800 V igbt，在100 A/cm/sup 2/下的V/sub (sat)/低至1.4 V。这种优异的性能是在不使用任何传统寿命控制技术的情况下实现的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Analysis of direct wafer bond IGBTs with heavily doped N+ buffer layer

High-speed IGBTs fabricated using direct wafer bonding and implanted N+ buffer layer are described and analyzed in this paper. The trade-off between on-state voltage drop and turn-off fall time can be controlled by varying the N+ implant dose prior to the wafer bonding process. 800 V IGBTs with switching time less than 100 nanoseconds and V/sub ce(sat)/ as low as 1.4 V at 100 A/cm/sup 2/ have been obtained. This excellent performance is achieved without utilizing any conventional lifetime control techniques.

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来源期刊

8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings

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