Design of Low Power & High Speed Approximate Compressor Based Multiplier

The most common arithmetic operation performed in digital electronics is the multiplication operation. Ranging from calculating products to processing of various media, multiplication is used in every process performed by digital circuits. The executable module found in the data path which performs the multiplication operation is the multiplier. Over the years, the improvement of multiplier’s efficiency has been a matter of discussion in digital electronics. The need for improving and optimising the area, power, delay characteristics of multipliers has been ever increasing due to electronics moving into a miniaturisation age. Various designs of multipliers have been proposed over the years in the attempts of achieving this need by improving every component such as the compressor that makes up the multiplier itself. It has also been found that many of the applications can allow errors but still give out usable results. This was known as the approximate computing paradigm. This paper contains designs of a set of approximate 4-2 compressors which will be then used to design multipliers. The multiplier designs proposed consist of approximate compressors alone and a combination of approximate and exact compressors. The various multipliers proposed have been compared with one another and other existing multipliers proposed by various authors. The paper further extends to image processing using the proposed multipliers in order to verify and analyse their performances using PSNR and SSIM values.