{"title":"低误差和面积效率的固定宽度乘法器使用小的输入校正向量","authors":"I-Chyn Wey, Chun-Chien Wang","doi":"10.1109/ICEIE.2010.5559909","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a new error compensation circuit by using dual group minor input correction vector to lower compensation error. By utilizing the symmetric property of MIC and construct the error compensation circuit mainly by the “outer” partial products, the hardware complexity can be lowered and only increases slightly as the multiplier input bits increase. In the proposed 16-bit fixed-width multiplier, the truncation error can be reduced by 87% as compared with the direct-truncated multiplier and the transistor counts can be reduced by 47% as compared with the full-length multiplier.","PeriodicalId":211301,"journal":{"name":"2010 International Conference on Electronics and Information Engineering","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2010-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Low-error and area-efficient fixed-width multiplier by using minor input correction vector\",\"authors\":\"I-Chyn Wey, Chun-Chien Wang\",\"doi\":\"10.1109/ICEIE.2010.5559909\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we propose a new error compensation circuit by using dual group minor input correction vector to lower compensation error. By utilizing the symmetric property of MIC and construct the error compensation circuit mainly by the “outer” partial products, the hardware complexity can be lowered and only increases slightly as the multiplier input bits increase. In the proposed 16-bit fixed-width multiplier, the truncation error can be reduced by 87% as compared with the direct-truncated multiplier and the transistor counts can be reduced by 47% as compared with the full-length multiplier.\",\"PeriodicalId\":211301,\"journal\":{\"name\":\"2010 International Conference on Electronics and Information Engineering\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-09-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 International Conference on Electronics and Information Engineering\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEIE.2010.5559909\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International Conference on Electronics and Information Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEIE.2010.5559909","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Low-error and area-efficient fixed-width multiplier by using minor input correction vector
In this paper, we propose a new error compensation circuit by using dual group minor input correction vector to lower compensation error. By utilizing the symmetric property of MIC and construct the error compensation circuit mainly by the “outer” partial products, the hardware complexity can be lowered and only increases slightly as the multiplier input bits increase. In the proposed 16-bit fixed-width multiplier, the truncation error can be reduced by 87% as compared with the direct-truncated multiplier and the transistor counts can be reduced by 47% as compared with the full-length multiplier.