{"title":"类osi分层NoC的事务级建模","authors":"S. Hamza Sfar, I. Bennour, R. Tourki","doi":"10.1109/DTIS.2006.1708669","DOIUrl":null,"url":null,"abstract":"The increasing of SoC complexity and the need of performance, encourage designers to implement network on chip rather than point to point connection or shared bus. NoC borrows many concepts to computer network and includes enough complexity to be transaction level modeled. But first, we must precise both system design flow and NoC characteristics to be modeled","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Transaction level modeling of an OSI-like layered NoC\",\"authors\":\"S. Hamza Sfar, I. Bennour, R. Tourki\",\"doi\":\"10.1109/DTIS.2006.1708669\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The increasing of SoC complexity and the need of performance, encourage designers to implement network on chip rather than point to point connection or shared bus. NoC borrows many concepts to computer network and includes enough complexity to be transaction level modeled. But first, we must precise both system design flow and NoC characteristics to be modeled\",\"PeriodicalId\":399250,\"journal\":{\"name\":\"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-10-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DTIS.2006.1708669\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DTIS.2006.1708669","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Transaction level modeling of an OSI-like layered NoC
The increasing of SoC complexity and the need of performance, encourage designers to implement network on chip rather than point to point connection or shared bus. NoC borrows many concepts to computer network and includes enough complexity to be transaction level modeled. But first, we must precise both system design flow and NoC characteristics to be modeled