RTL Design for Time Efficient DDR3 Memory Interfaced with RTG4 FPGA

The new age of remote detecting instrument typically creates a gigantic measure of information, which must be transmitted to the earth station for handling. In this paper, a RTL Design is proposed in Libero SP3 Microsemi Software for data processing. This design contains FDDR memory controller of DDR3 memory of RTG4 FPGA. The interfacing of memory controller and user module is done by AXI (Advanced eXtensible Interface) Bus having 64 bit data-bus and 32 bit address-bus. Input data frequency is 160MHz and the output data rate is 320Mbps as in DDR3 memory data transfer done in burst format and also in both the clock edges. The proposed design is synthesizable and also verified with simulation result in Microsemi ModelSim Pro. From result it is analyzed that the read time is reduced by 46% then write time.