基于级联编码翻转电压从动器的soc无输出电容低差稳压器

Guangxiang Li, Jianping Guo, Yanqi Zheng, Mo Huang, Dihu Chen
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引用次数: 5

摘要

提出了一种新型的基于级联编码翻转电压从动器(CAFVF)的无输出电容低差(LDO)稳压器,并在0.18 μm CMOS工艺上实现。通过将级联码电流源(CCS)嵌入到CAFVF结构中,所提出的LDO稳压器在重负载条件下(100 mA)可实现58.6 db DC增益,而在相同条件下,传统CAFVF对应器件的增益为44 db。引入级联补偿技术,拓宽环路带宽,降低最小负载要求。采用5-pF补偿电容,保持LDO稳压器稳定的最小负载电流降至50 μA。此外,在100 ma负载条件下,单位增益频率(UGF)从1.51 MHz扩展到2.36 MHz。此外,在不忽略任何通道阻力的情况下,本文给出了精确的稳定性分析。仿真结果表明,LDO稳压器在1.2 V ~ 1.8 V的输入电压范围内消耗14 μA的超低静态电流(Iq),电压降为200 mV。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Cascoded flipped voltage follower based output-capacitorless low-dropout regulator for SoCs
A novel cascoded flipped voltage follower (CAFVF) based output-capacitorless low-dropout (LDO) regulator is proposed and implemented in 0.18-μm CMOS technology. With a cascode current source (CCS) embedded into the CAFVF structure, the proposed LDO regulator achieves 58.6-dB DC gain in heavy loading condition (100 mA), which is 44-dB for the conventional CAFVF counterpart under identical conditions. The cascode compensation technique is introduced to widen the loop bandwidth and reduce the minimal loading requirement. With a 5-pF compensation capacitor, the minimum load current to keep the proposed LDO regulator stable is reduced to 50 μA. In addition, the unity-gain frequency (UGF) is extended from 1.51 MHz to 2.36 MHz in 100-mA loading condition. Moreover, an accurate stability analysis without ignoring any channel resistance has been presented in this work. Simulation results show that the LDO regulator consumes an ultra-low quiescent current (Iq) of 14 μA for input voltage ranging from 1.2 V to 1.8 V, with a dropout voltage (Vdrop) of 200 mV.
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