{"title":"具有8级静态电流源控制的低能量流水线多值电流模式电路","authors":"M. Natsui, T. Arimitsu, T. Hanyu","doi":"10.1109/ISMVL.2010.51","DOIUrl":null,"url":null,"abstract":"A static current-source control technique in a multiple-valued current-mode (MVCM) circuit is proposed for a low-energy pipelined system. A current-control block embedded in each pipeline stage generates current control signals, which minimizes the amount of current flows depending on a given condition. The use of this current-source control technique makes it possible to reduce the power dissipation with maintaining the operating frequency. The efficiency of the proposed technique in a pipelined MVCM multiplier is confirmed by using HSPICE simulation under 0.13um CMOS technology. The MVCM circuit using the proposed technique achieves 65.1% power reduction compared with a conventional MVCM implementation at the operating frequency of 100MHz and 26.5% reduction at 500MHz with 6.88% area overhead.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Low-Energy Pipelined Multiple-Valued Current-Mode Circuit with 8-Level Static Current-Source Control\",\"authors\":\"M. Natsui, T. Arimitsu, T. Hanyu\",\"doi\":\"10.1109/ISMVL.2010.51\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A static current-source control technique in a multiple-valued current-mode (MVCM) circuit is proposed for a low-energy pipelined system. A current-control block embedded in each pipeline stage generates current control signals, which minimizes the amount of current flows depending on a given condition. The use of this current-source control technique makes it possible to reduce the power dissipation with maintaining the operating frequency. The efficiency of the proposed technique in a pipelined MVCM multiplier is confirmed by using HSPICE simulation under 0.13um CMOS technology. The MVCM circuit using the proposed technique achieves 65.1% power reduction compared with a conventional MVCM implementation at the operating frequency of 100MHz and 26.5% reduction at 500MHz with 6.88% area overhead.\",\"PeriodicalId\":447743,\"journal\":{\"name\":\"2010 40th IEEE International Symposium on Multiple-Valued Logic\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-05-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 40th IEEE International Symposium on Multiple-Valued Logic\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL.2010.51\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 40th IEEE International Symposium on Multiple-Valued Logic","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.2010.51","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Low-Energy Pipelined Multiple-Valued Current-Mode Circuit with 8-Level Static Current-Source Control
A static current-source control technique in a multiple-valued current-mode (MVCM) circuit is proposed for a low-energy pipelined system. A current-control block embedded in each pipeline stage generates current control signals, which minimizes the amount of current flows depending on a given condition. The use of this current-source control technique makes it possible to reduce the power dissipation with maintaining the operating frequency. The efficiency of the proposed technique in a pipelined MVCM multiplier is confirmed by using HSPICE simulation under 0.13um CMOS technology. The MVCM circuit using the proposed technique achieves 65.1% power reduction compared with a conventional MVCM implementation at the operating frequency of 100MHz and 26.5% reduction at 500MHz with 6.88% area overhead.