用于具有偶数级的可重新排列Log2(N, 0, p)结构的FPGA控制器

2011 IEEE 12th International Conference on High Performance Switching and Routing Pub Date : 2011-07-04 DOI:10.1109/HPSR.2011.5986003

W. Kabaciński, M. Michalski

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引用次数: 4

摘要

本文提出了一种可重新排列的log2(N, 0, p)交换结构，并给出了偶阶情况下的控制算法。本文的主要课题是实现这种结构的硬件控制器。该算法用VHDL代码描述，并在Xilinx公司的Virtex 5 - FGPA芯片演示板ML505上实现。这里介绍的实现工作速度非常快，控制器可以在发出请求后仅20纳秒就发出一组实际信号。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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FPGA controller for rearrangeable Log2(N, 0, p) fabrics with an even number of stages

In this paper we present rearrangeable log2(N, 0, p) switching fabrics and the control algorithm for the case of an even number of stages. The main topic of this paper is the implementation of a hardware controller for such fabrics. The algorithm is described in VHDL code and realized in ML505 - the demo board for Virtex 5 - FGPA chip from the Xilinx Company. The implementation presented here works very fast, the controller can send out the set of actual signals just 20 nanoseconds after the request has been made.

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来源期刊

2011 IEEE 12th International Conference on High Performance Switching and Routing

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