{"title":"纳米CMOS工艺中块驱动亚阈值差分对的Gm增强","authors":"L. H. C. Ferreira, S. Sonkusale","doi":"10.1109/SUBVT.2012.6404320","DOIUrl":null,"url":null,"abstract":"In this paper a simple and efficient way to enhance the transconductance Gm for bulk-driven sub-threshold differential pair in nanometer CMOS process is presented. This approach is based on a type of positive feedback source degeneration, which does not depend on geometry parameters or biasing voltages, and leads to improved values for the DC gain and the unity gain frequency, without increasing power consumption or changing other features. Despite of possible differential pair output resistance variation, the DC gain and the unity gain frequency of weak inversion differential pair can be increased by (n + 1)/(n - 1) times (e.g., 13.72 times in an 130-nm IBM CMOS process), a factor that improves with scaling while many other device characteristics degrade.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"58 4","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"Gm enhancement for bulk-driven sub-threshold differential pair in nanometer CMOS process\",\"authors\":\"L. H. C. Ferreira, S. Sonkusale\",\"doi\":\"10.1109/SUBVT.2012.6404320\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper a simple and efficient way to enhance the transconductance Gm for bulk-driven sub-threshold differential pair in nanometer CMOS process is presented. This approach is based on a type of positive feedback source degeneration, which does not depend on geometry parameters or biasing voltages, and leads to improved values for the DC gain and the unity gain frequency, without increasing power consumption or changing other features. Despite of possible differential pair output resistance variation, the DC gain and the unity gain frequency of weak inversion differential pair can be increased by (n + 1)/(n - 1) times (e.g., 13.72 times in an 130-nm IBM CMOS process), a factor that improves with scaling while many other device characteristics degrade.\",\"PeriodicalId\":383826,\"journal\":{\"name\":\"2012 IEEE Subthreshold Microelectronics Conference (SubVT)\",\"volume\":\"58 4\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE Subthreshold Microelectronics Conference (SubVT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SUBVT.2012.6404320\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SUBVT.2012.6404320","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Gm enhancement for bulk-driven sub-threshold differential pair in nanometer CMOS process
In this paper a simple and efficient way to enhance the transconductance Gm for bulk-driven sub-threshold differential pair in nanometer CMOS process is presented. This approach is based on a type of positive feedback source degeneration, which does not depend on geometry parameters or biasing voltages, and leads to improved values for the DC gain and the unity gain frequency, without increasing power consumption or changing other features. Despite of possible differential pair output resistance variation, the DC gain and the unity gain frequency of weak inversion differential pair can be increased by (n + 1)/(n - 1) times (e.g., 13.72 times in an 130-nm IBM CMOS process), a factor that improves with scaling while many other device characteristics degrade.