基于纳米级低功率泄漏st的SRAM

2012 International Conference on Emerging Trends in Electrical Engineering and Energy Management (ICETEEEM) Pub Date : 2012-12-01 DOI:10.1109/ICETEEEM.2012.6494475

K. Amalraj, P. Sathishkumar, K. Vigneshraja, N. Arunkumar, C. A. Anjo

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引用次数: 2

摘要

本文工作的主要目的是在180*10-9m的SRAM电路中减少漏功率，并在较低的电源电压下产生稳定的输出。一般来说，传统SRAM电路的功耗较高。为了克服这一问题，介绍了一种基于施密特触发器(ST)的新型SRAM电路，其功耗比传统SRAM低得多。本文采用SOI-DTMOS(绝缘体上硅-动态阈值MOS)，以保证供电电压低和运行稳定。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Nano scaled low power leakage st-based SRAM

The main purpose of this paper work is to reduce leakage power and to produce stable output at lower supply voltages for SRAM circuits in 180*10-9m. Generally the power dissipation in conventional SRAM circuits will be high. In order to overcome that problem, a new SRAM circuit based on Schmitt trigger (ST) is introduced which consumes very less power than conventional SRAMs. Here SOI-DTMOS (Silicon on insulator-dynamic threshold MOS) are utilized in order to have low supply voltage and stability during operations.

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来源期刊

2012 International Conference on Emerging Trends in Electrical Engineering and Energy Management (ICETEEEM)

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