{"title":"一种兼容CMOS的低功耗超密电容无SOI RAM","authors":"P. Fazan, S. Okhonin, M. Nagoga","doi":"10.1109/ISDRS.2003.1272147","DOIUrl":null,"url":null,"abstract":"This paper presents low power writing mechanisms for the ultra dense capacitor less RAM cell on SOI (silicon-on-insulator). By exploiting band to band tunneling and negative voltages, no current flows in the cell during writing and large programming windows is obtained. First results on data disturb is presented. evidence of a charge pumping related related gate disturb is shown.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"269 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A CMOS compatible low power ultra dense capacitor less SOI RAM\",\"authors\":\"P. Fazan, S. Okhonin, M. Nagoga\",\"doi\":\"10.1109/ISDRS.2003.1272147\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents low power writing mechanisms for the ultra dense capacitor less RAM cell on SOI (silicon-on-insulator). By exploiting band to band tunneling and negative voltages, no current flows in the cell during writing and large programming windows is obtained. First results on data disturb is presented. evidence of a charge pumping related related gate disturb is shown.\",\"PeriodicalId\":369241,\"journal\":{\"name\":\"International Semiconductor Device Research Symposium, 2003\",\"volume\":\"269 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-12-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Semiconductor Device Research Symposium, 2003\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISDRS.2003.1272147\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Semiconductor Device Research Symposium, 2003","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISDRS.2003.1272147","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A CMOS compatible low power ultra dense capacitor less SOI RAM
This paper presents low power writing mechanisms for the ultra dense capacitor less RAM cell on SOI (silicon-on-insulator). By exploiting band to band tunneling and negative voltages, no current flows in the cell during writing and large programming windows is obtained. First results on data disturb is presented. evidence of a charge pumping related related gate disturb is shown.