包括HDL和合成在EE和CSE数字设计课程

K. Chang
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引用次数: 8

摘要

随着小尺寸半导体工艺技术的出现,数字设计的复杂性急剧增加。这种增长对行业提出了巨大的需求,产生了硬件描述语言(HDL),它以基于HDL的设计过程、方法和设计工具作为回应。HDL不仅管理增加的复杂性,而且还允许更短的设计周期。在数字设计课程中加入HDL和合成将面临挑战。本文针对这些挑战提出了一些建议。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Including HDL and synthesis in the EE and CSE digital design curriculum
The complexity of digital designs has increased drastically with the advent of the smaller geometry semiconductor process technology. This increase has made enormous demands on the industry, giving rise to Hardware Description Languages (HDL) which responded with its HDL-based design process, methodology, and design tools. HDL not only manages the increased complexity, but it also allows a shorter design cycle. Including HDL and synthesis in digital design curriculums will have its challenges. This paper addresses those challenges and proposes some recommendations.
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