{"title":"一种用于无线内镜胶囊的低功耗CMOS图像传感器设计","authors":"Milin Zhang, A. Bermak, Xiaowen Li, Zhihua Wang","doi":"10.1109/BIOCAS.2008.4696958","DOIUrl":null,"url":null,"abstract":"This paper proposes a low power full-custom CMOS digital pixel sensor array designed for a wireless endoscopy capsule. The proposed architecture greatly reduces the on-chip memory requirement by sharing pixel-level memory in the sensor array with the digital image processor. The pixel-level memories in the proposed full-custom image sensor are used not only to store the raw image pixel values in the image capture phase, but also is also used as buffers for the digital image processor during the image compression and transmission phase. Low power design is carried out both at the algorithmic and circuit levels, which reduces almost 50% switching activities on data bus, about 80% of power consumption in the main pixel circuit during image capture phase and 15% during image process phase while transmitting data at a rate of 2-frame/s.","PeriodicalId":415200,"journal":{"name":"2008 IEEE Biomedical Circuits and Systems Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"28","resultStr":"{\"title\":\"A low power CMOS image sensor design for wireless endoscopy capsule\",\"authors\":\"Milin Zhang, A. Bermak, Xiaowen Li, Zhihua Wang\",\"doi\":\"10.1109/BIOCAS.2008.4696958\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a low power full-custom CMOS digital pixel sensor array designed for a wireless endoscopy capsule. The proposed architecture greatly reduces the on-chip memory requirement by sharing pixel-level memory in the sensor array with the digital image processor. The pixel-level memories in the proposed full-custom image sensor are used not only to store the raw image pixel values in the image capture phase, but also is also used as buffers for the digital image processor during the image compression and transmission phase. Low power design is carried out both at the algorithmic and circuit levels, which reduces almost 50% switching activities on data bus, about 80% of power consumption in the main pixel circuit during image capture phase and 15% during image process phase while transmitting data at a rate of 2-frame/s.\",\"PeriodicalId\":415200,\"journal\":{\"name\":\"2008 IEEE Biomedical Circuits and Systems Conference\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"28\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE Biomedical Circuits and Systems Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BIOCAS.2008.4696958\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE Biomedical Circuits and Systems Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIOCAS.2008.4696958","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A low power CMOS image sensor design for wireless endoscopy capsule
This paper proposes a low power full-custom CMOS digital pixel sensor array designed for a wireless endoscopy capsule. The proposed architecture greatly reduces the on-chip memory requirement by sharing pixel-level memory in the sensor array with the digital image processor. The pixel-level memories in the proposed full-custom image sensor are used not only to store the raw image pixel values in the image capture phase, but also is also used as buffers for the digital image processor during the image compression and transmission phase. Low power design is carried out both at the algorithmic and circuit levels, which reduces almost 50% switching activities on data bus, about 80% of power consumption in the main pixel circuit during image capture phase and 15% during image process phase while transmitting data at a rate of 2-frame/s.