Exploring the Potential of Error-permissive Communication in Multi-FPGA-based Edge Computing

In recent years, Edge Computing has been attracting a lot of attention as it has shown its ability to mitigate some issues found in Cloud Computing (e.g., high latency, centralization issues, programmability, etc.), Moving computation from the Cloud to the Edge has resulted in an exponential increase in the number of devices to be connected. With such an increase, interconnection has become a major design and performance factor, especially in terms of power efficiency. Thus, the question that a lot of research has been trying to answer is how to connect such devices in a power-efficient way while making sure to maintain high-performance and accuracy at the lowest cost. In this paper, we investigate the Error-permissive communication paradigm and its potential to answer the aforementioned question. In particular, we focus on the importance of using this paradigm on Multi-FPGA systems which have gained significant attention in Edge Computing and can be a good candidate for Error-permissive communication. We also present a preliminary evaluation of a novel concept to reduce the power consumption by undervolting the supply voltage of the serial transceivers, and we show its potential to reduce the total FPGA power consumption by up to 26%.