A holistic approach for building MPSoCs

Multi-Processor Systems-on-a-chip (MPSoCs) are currently the most common implementation technique to build complex systems that provide high performance according to both timing and power restrictions for electronic systems. Both many-core (usually homogeneous multiprocessing) and multi-core (more often heterogeneous) require providing some complex parallel programming methods together with architectural exploration and performance analysis tools to get into an optimal solution. The concept of network-on-chip and programming model topics on multiprocessors system-on-chip world will be reviewed using some selected proposals to highlight the evolution of the implementation approaches. FPGAs are being used to prototype these complex systems since they provide a high degree of visibility of the system activity at different levels of abstraction. The emerging Reconfigurable Hardware devices allow the design of complex embedded systems combining soft-core processors and a mix of other IP cores. The reduced NRE costs compared to ASIC is a typical reason to choose FPGAs as a platform to implement some applications. But the continuous increase of capacity, and the flexibility offered by reconfigurable hardware, are also important reasons to select FPGAs in order to get good Time-to-Market and Time-in-Market values. Furthermore, and because of this existing infrastructure, FPGAs can provide multi-soft-core solutions are a viable suppose and interesting solutions for embedded systems that naturally appear after new general purpose platforms. These embedded systems are therefore oriented to specific purpose applications and need some additional trade-off between performance, flexibility and development time. FPGAs allows that, at a reasonable cost, we will have available many-soft-cores solutions so that they are expected to have some relevance for some future embedded systems. Then, in addition to the current soft-core SoC tools, some parallel programming methods and tools will be required as a part of the full system development process. Performance analysis tools have also to be updated taking into account specificities of parallel programming (most of them coming from the high performance computing community) has a critical part of the development process for parallel embedded applications. Meeting some real-time constraints is a critical issue when you want to get a desired performance. A basic review of the techniques used by the HPC community will be reviewed such as the post-mortem analysis of application traces, taking into account the resource limitations of the FPGA platforms for embedded systems. This review will include several techniques and some Hardware architectural support to be able to generate traces on multiprocessor systems based on FPGAs and use them to optimize the performance of the running applications. Finally, soft-cores allow an additional advantage due to the fact that one can easily add hardware acceleration or improve communications performance, as usual bottlenecks to reach performance constraints, by using ad-hoc solutions coming from the analysis of the system behavior at different levels of abstraction (from parallel programming down to node activities). QoS techniques, also added to some of the programming methods to dynamically cope with performance, will also be reviewed.