{"title":"一种具有假填充的超宽带CMOS PA,以提高可靠性","authors":"Yu-Ting Chang, Y. Ye, C. Domier, Q. Gu","doi":"10.1109/IEEE-IWS.2015.7164562","DOIUrl":null,"url":null,"abstract":"This paper presents a V-band power amplifier in a bulk 65 nm CMOS technology with the peak gain 14.5 dB and 3-dB bandwidth of 28.8 GHz (50.8 GHz to 79.6 GHz). The PA has demonstrated 15.1 dBm Psat and 18.9 % peak PAE. The PA features three stage transformer coupled differential architecture with integrated input and output baluns. The entire PA core occupies 0.31 mm2 chip area and dissipates about 150 mW.","PeriodicalId":164534,"journal":{"name":"2015 IEEE International Wireless Symposium (IWS 2015)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A ultra-wideband CMOS PA with dummy filling for reliability\",\"authors\":\"Yu-Ting Chang, Y. Ye, C. Domier, Q. Gu\",\"doi\":\"10.1109/IEEE-IWS.2015.7164562\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a V-band power amplifier in a bulk 65 nm CMOS technology with the peak gain 14.5 dB and 3-dB bandwidth of 28.8 GHz (50.8 GHz to 79.6 GHz). The PA has demonstrated 15.1 dBm Psat and 18.9 % peak PAE. The PA features three stage transformer coupled differential architecture with integrated input and output baluns. The entire PA core occupies 0.31 mm2 chip area and dissipates about 150 mW.\",\"PeriodicalId\":164534,\"journal\":{\"name\":\"2015 IEEE International Wireless Symposium (IWS 2015)\",\"volume\":\"109 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-07-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE International Wireless Symposium (IWS 2015)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEEE-IWS.2015.7164562\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Wireless Symposium (IWS 2015)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEEE-IWS.2015.7164562","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A ultra-wideband CMOS PA with dummy filling for reliability
This paper presents a V-band power amplifier in a bulk 65 nm CMOS technology with the peak gain 14.5 dB and 3-dB bandwidth of 28.8 GHz (50.8 GHz to 79.6 GHz). The PA has demonstrated 15.1 dBm Psat and 18.9 % peak PAE. The PA features three stage transformer coupled differential architecture with integrated input and output baluns. The entire PA core occupies 0.31 mm2 chip area and dissipates about 150 mW.