On designing optimal camouflaged layouts

Integrated circuit (IC) camouflaging is a layout-level technique that hampers reverse-engineering attacks. In one embodiment of camouflaging, layouts of different Boolean gates are designed to look alike by using a combination of true and dummy contacts. The security of IC camouflaging using dummy contacts depends on an attackers inability to determine whether a contact is true or dummy. The layouts of camouflaged gates in prior works incur tremendous overhead: 4x in area, 5.5x in power, and 1.8x in delay. Thus, overhead is a major impediment to adoption of IC camouflaging. To solve this problem, we propose an algorithm to generate the layouts of camouflaged gates using dummy contacts for static CMOS logic. In this work, we develop low-cost camouflaging solutions using a graph-theoretic approach. Given an optimization objective and a list of Boolean functions whose layouts have to look alike, the proposed algorithm produces look-alike layouts that are optimized (minimized) in terms of area, power, delay, or a combination. Results indicate that the proposed design is more robust against variations and has better noise margin than the existing techniques.