M. Mohammadi, Rohit Ronge, J. Chandiramani, S. Nandy
{"title":"基于径向基函数神经网络的分类加速器","authors":"M. Mohammadi, Rohit Ronge, J. Chandiramani, S. Nandy","doi":"10.1109/SOCC.2015.7406928","DOIUrl":null,"url":null,"abstract":"A scalable and reconfigurable architecture for accelerating classification using Radial Basis Function Neural Network (RBFNN) is presented in this paper. The proposed accelerator comprises a set of interconnected HyperCells, which serve as the reconfigurable datapath on which the RBFNN is realized. The dimensions of RBFNN that can be supported on implemented design is limited due to the fixed number of HyperCells. To resolve this limitation, a folding strategy is discussed which provides a generic hardware solution for classification using RBFNN, with no constraint on the dimensions of inputs and outputs. The performance of RBFNN implemented on network of HyperCells using Xilinx Virtex 7 XC7V2000T as target FPGA is compared with software implementation and GPU implementation of RBFNN. Our results show speed up of 1.91X-15.94X over equivalent software implementation on Intel Core 2 Quad and 1.33X-14.6X over GPU (NVIDIA GTX650).","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"112 8","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"An accelerator for classification using radial basis function neural network\",\"authors\":\"M. Mohammadi, Rohit Ronge, J. Chandiramani, S. Nandy\",\"doi\":\"10.1109/SOCC.2015.7406928\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A scalable and reconfigurable architecture for accelerating classification using Radial Basis Function Neural Network (RBFNN) is presented in this paper. The proposed accelerator comprises a set of interconnected HyperCells, which serve as the reconfigurable datapath on which the RBFNN is realized. The dimensions of RBFNN that can be supported on implemented design is limited due to the fixed number of HyperCells. To resolve this limitation, a folding strategy is discussed which provides a generic hardware solution for classification using RBFNN, with no constraint on the dimensions of inputs and outputs. The performance of RBFNN implemented on network of HyperCells using Xilinx Virtex 7 XC7V2000T as target FPGA is compared with software implementation and GPU implementation of RBFNN. Our results show speed up of 1.91X-15.94X over equivalent software implementation on Intel Core 2 Quad and 1.33X-14.6X over GPU (NVIDIA GTX650).\",\"PeriodicalId\":329464,\"journal\":{\"name\":\"2015 28th IEEE International System-on-Chip Conference (SOCC)\",\"volume\":\"112 8\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 28th IEEE International System-on-Chip Conference (SOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC.2015.7406928\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 28th IEEE International System-on-Chip Conference (SOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2015.7406928","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An accelerator for classification using radial basis function neural network
A scalable and reconfigurable architecture for accelerating classification using Radial Basis Function Neural Network (RBFNN) is presented in this paper. The proposed accelerator comprises a set of interconnected HyperCells, which serve as the reconfigurable datapath on which the RBFNN is realized. The dimensions of RBFNN that can be supported on implemented design is limited due to the fixed number of HyperCells. To resolve this limitation, a folding strategy is discussed which provides a generic hardware solution for classification using RBFNN, with no constraint on the dimensions of inputs and outputs. The performance of RBFNN implemented on network of HyperCells using Xilinx Virtex 7 XC7V2000T as target FPGA is compared with software implementation and GPU implementation of RBFNN. Our results show speed up of 1.91X-15.94X over equivalent software implementation on Intel Core 2 Quad and 1.33X-14.6X over GPU (NVIDIA GTX650).