Compact Modeling of IGZO-based CAA-FETs with Time-zero-instability and BTI Impact on Device and Capacitor-less DRAM Retention Reliability

This work developed a compact model of the stackable vertical Channel-All-Around (CAA) IGZO FETs, based on carrier trapping dynamics and (inner/outer) surface potential of a cylindrical channel shell. It is calibrated to fabricated devices with geometric effects (e.g., asymmetry Source/Drain (S/D) to Gate (G) overlaps) on turn-on voltage (Von). Besides, temperature (T) effects on Von, leakage current and non-linear contacts were considered from 233 K to 393 K, and such degradation effects contribute to time-zero instability (TZI) on DRAM retention performance. To further understand time dependent reliability (i.e., bias-temperature-instability, BTI), an abnormal PBTI with negative Von shift is studied from the perspective of device physics and is more pronounced than NBTI. By incorporating TZI and BTI in capacitor-less DRAMs, it enables a reliability-aware design technology co-optimization flow characterizing weak cells for scalability of BEOL-compatible 3D integration.