A fast and accurate logarithm accelerator for scientific applications

Many scientific applications rely on evaluation of elementary functions. Nowadays, high-level programming languages provide their own elementary function libraries in software by using lookup table and/or polynomial approximation. However, one downside is slow since lookup tables could keep cache thrashing and polynomial approximations require a number of iterations to converge. Thus, elementary functions evaluation becomes bottleneck for most scientific applications. With this motivation, we propose a generalized pipelined hardware architecture for elementary functions to accelerate scientific applications. This paper presents a pipelined, single precision logarithm hardware accelerator (SP-LHA). Throughput of SP-LHA is at least 2.5GFLOPS in 65nm ASICs, while the circuit consists of ≈60,000 logic gates. Average accuracy of SP-LHA is 22.5 out of 23 bits, which is achieved by using 7.8KB lookup table and parabolic interpolation.