A CMOS MedRadio-band low-power integer-N cascaded phase-locked loop for implantable medical SOCs

In this paper, a low power integer-N cascaded Phase-locked loop (PLL) is proposed to provide the carrier signal and clock signals for a SOC with MedRadio-band transceiver, ADC, DSP, and 13.56-MHz wireless power supply. In the proposed cascaded PLL, the first PLL provides the sampling clocks while the second PLL provides the carrier clock. Furthermore, the 13.56-MHz signal from the receiving coil of the wireless power transmission system is utilized as the input reference signal. Ring-based voltage controlled oscillator (VCO) is designed to minimize both power consumption and chip area. The proposed cascaded PLL is designed and implemented in 0.18-μm CMOS technology. The measured phase noise is -79 dBc/Hz at 100 kHz offset under 402.9 MHz. The measured power consumptions are 0.28 mW in the first PLL and 0.46mW in the second PLL with a 1.8V supply voltage. The proposed cascaded PLL has low power dissipation, small chip area, and no off-chip components or crystal oscillator. It is suitable for the integration with implantable medical SOCs.