A 0.14-3.5 GHz All Digital PLL with improved fast frequency-lock and a novel TDC-based self-calibration capability

An AD-PLL with a self-calibrated hierarchical Time to Digital Converter (TDC) is proposed to attain a wide range of operation and a phase error monitor to reduce the process lock. To cover a wide range of frequency with improved spectral purity, two digitally controlled oscillators are proposed. An LC-tank oscillator with a tunable active inductor is used to reach the on-GHz band with a fine tuning resolution, while the sub-GHz is covered by an interpolated ring DCO. The proposed ADPLL is designed using a 90 nm TSMC CMOS process. The operational frequency range of the proposed circuit varies from 140 MHz to 3.52 GHz. The ADPLL achieves a fast settling time of less than 5 μs. By consuming 13.4 mW, the frequency synthesizer achieves -105 dBc/Hz far-off phase noise and -55 dBc fractional spur.