为TRON架构优化C编译器

K. Matsunami, T. Yamana, H. Ito
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引用次数: 0

摘要

讨论了用于实时操作系统核心TRON架构的GMICRO F32系列32位微处理器的优化C编译器的开发及其效果。TRON架构的编译器优化,或CISC(复杂指令集计算机)架构具有其独特的特点,是通过澄清增加的执行速度和减少的对象大小之间的冲突(权衡)来实现的,以产生优化的C编译器。特别是在执行速率和对象大小上采用“1:2规则”,实现了该CISC体系结构的编译器优化。这个优化的C语言编译器将实现用C语言编写的多种应用程序在TRON架构中的应用。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Optimizing C compiler for the TRON architecture
A discussion is given on the development and effects of an optimizing C compiler for the GMICRO F32 series of 32 bit microprocessors which are available for the TRON (the real time operating system nucleus) architecture. Compiler optimizations for the TRON architecture, or the CISC (complex instruction set computer) architecture with its distinct features, were achieved through a clarification of the conflict (trade-off) between the increased execution rate and the reduced object size to produce an optimizing C compiler. In particular, the application of the '1:2 rule' to the execution rate and the object size achieved the compiler optimization for this CISC architecture. That this optimizing C compiler will accomplish the objective of applying many types of application programs written in C language to the TRON architecture.<>
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