DC-40 GHz DPDT Switch Matrix Design with Novel Device in 300mm RFSOI

This paper presents low insertion loss, high isolation, ultra wideband double-pole-double-throw (DPDT) switch matrix designed with novel device structures in a commercial $0.13\ \mu\mathrm{m}$ high resistivity trap-rich SOI. The switches are designed using series-shunt-series configuration in a ring-type with input and output matching networks. The designed switches achieve widest bandwidth from DC to 40 GHz with a low insertion loss of less than 3 dB and a high isolation of 34 dB up to 40 GHz. The high performance DPDT switch is fabricated via selective SOI top silicon thinning. It was found SOI top silicon recess can significantly improve the DPDT switch insertion loss. The active chip area of designed $2\times 2$ switch matrix is only $0.28 \text{mm}\times 0.21\ \text{mm}$.