Memory, control and communications synthesis for scheduled algorithms

A problem of memory allocation for intermediate variables in an ASIC synthesis system is addressed. A method is explored of grouping individual memory requirements from a hardware-constrained schedule of an algorithm, such that control and communications may be optimized. A new representation of memory requirements is introduced to explain the method. The technique may also be used to allocate operations to hardware resources. This, and control and communication optimization are illustrated with an example.<>