A Modified Signal Reconstruction Method in Low Feedback Sampling Rate Digital Predistortion

Digital predistortion (DPD) is an effective way to optimize the linearization of power amplifiers (PAs). The sampling rate of the feedback loop generally requires five times the input signal bandwidth due to the spectrum expansion, which results in great challenges of analog-to-digital converters (ADCs). An improved method in low feedback sampling rate DPD architecture is proposed in this paper to reduce the computational complexity of the downsampling DPD. By interpolating the low sampling output signal, the proposed method greatly reduces the algorithm complexity in terms of time alignment. In addition, an improved model containing fractional exponential power functions are presented to obtain higher modeling accuracy. To validate the proposed methods, simulations and experiments are performed respectively. With the downsampling rate of 100, the convergence speed of the proposed alignment algorithm is 10 times that of the traditional one, and the adjacent channel power ratio (ACPR) is improved by 3dB after predistortion.