30mW 12b 21MSample/s流水线CMOS ADC

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.993057

S. Kulhalli, V. Penkota, R. Asv

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引用次数: 17

摘要

一个0.6/spl mu/m双聚CMOS 12b ADC采用多种不同的技术来获得低功耗。ADC在21 MSample/s下实现68dB信噪比，在2.7V下消耗30mW。模具面积2.56mm/sup 2/。

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A 30mW 12b 21MSample/s pipelined CMOS ADC

A 0.6/spl mu/m double-poly CMOS 12b ADC uses a number of different techniques to obtain low power. The ADC achieves 68dB SNR at 21 MSample/s, consuming 30mW at 2.7V. Die area is 2.56mm/sup 2/.

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2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

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