ULSI封装中的电气建模和仿真问题

J. Prince
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引用次数: 0

摘要

只提供摘要形式。建模和仿真能力是尚未开发的ULSI设计系统的关键组件。该领域的问题围绕着执行有效仿真的关键能力,即在设计工程师以信息格式获得可接受的准确结果之前,以最小的实时延迟进行仿真。这其中隐含的前提是,永远没有足够的计算和信息管理能力来完全分析(没有近似或截断)与人类设计工程实践一致的实际设计。讨论了不同电分析域之间边界的探索和定义。设计数据操作和信息管理对于涉及几十个芯片,数千个I/O和数万条互连线的系统至关重要,当芯片I/O计数和互连线计数增加一到两个数量级时,这将成为一个更大的问题,也被考虑在内。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Electrical modeling and simulation issues in ULSI packaging
Summary form only given. Modeling and simulation capabilities are key components ULSI design systems yet to be developed. Issues in this area revolve around the critical ability to perform efficient simulation, i.e., the simulation with the least real-time delay before acceptably accurate results are available to the design engineer in an information format. Implicit in this is the premise that there is never enough computational and information management capability to fully analyze (no approximations or truncations) real designs in times consistent with human design engineering practice. The exploration and definition of the boundaries between different electrical analysis domains were discussed. Design data manipulation and information management, which are critical for systems involving a few dozen chips with a few thousand I/Os and a few tens of thousands of interconnect lines and which will become more of an issue when the chip I/O count and interconnect line count increase by one or two orders of magnitude, were also considered.<>
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