在ESD设计布局中建立可靠性

T. Yeoh
{"title":"在ESD设计布局中建立可靠性","authors":"T. Yeoh","doi":"10.1109/IPFA.1997.638192","DOIUrl":null,"url":null,"abstract":"Building in reliability during ESD design layout is key to the success of product design and development. Due to the limitations of automated layout checkers for ESD, knowledge of fundamental device physics, ESD and stress environments are essential.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Building in reliability during ESD design layout\",\"authors\":\"T. Yeoh\",\"doi\":\"10.1109/IPFA.1997.638192\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Building in reliability during ESD design layout is key to the success of product design and development. Due to the limitations of automated layout checkers for ESD, knowledge of fundamental device physics, ESD and stress environments are essential.\",\"PeriodicalId\":159177,\"journal\":{\"name\":\"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-07-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IPFA.1997.638192\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA.1997.638192","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

在ESD设计布局中建立可靠性是产品设计和开发成功的关键。由于静电放电自动布局检查器的局限性,了解基本的器件物理、静电放电和应力环境是必不可少的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Building in reliability during ESD design layout
Building in reliability during ESD design layout is key to the success of product design and development. Due to the limitations of automated layout checkers for ESD, knowledge of fundamental device physics, ESD and stress environments are essential.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信