{"title":"多终端设备的程序测试模式","authors":"Francis J. McIntosh, W. Happ","doi":"10.1145/1476793.1476831","DOIUrl":null,"url":null,"abstract":"The rapid development of micro-electronics towards multiterminal structures demands corresponding growth in understanding the potential and limitations of multiterminal devices and networks. The increasing sophistication of integrated circuits will impose a new set of criteria upon network synthesis.","PeriodicalId":326625,"journal":{"name":"AFIPS '69 (Spring)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1969-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Programmed test patterns for multiterminal devices\",\"authors\":\"Francis J. McIntosh, W. Happ\",\"doi\":\"10.1145/1476793.1476831\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The rapid development of micro-electronics towards multiterminal structures demands corresponding growth in understanding the potential and limitations of multiterminal devices and networks. The increasing sophistication of integrated circuits will impose a new set of criteria upon network synthesis.\",\"PeriodicalId\":326625,\"journal\":{\"name\":\"AFIPS '69 (Spring)\",\"volume\":\"42 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1969-05-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"AFIPS '69 (Spring)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/1476793.1476831\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"AFIPS '69 (Spring)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1476793.1476831","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Programmed test patterns for multiterminal devices
The rapid development of micro-electronics towards multiterminal structures demands corresponding growth in understanding the potential and limitations of multiterminal devices and networks. The increasing sophistication of integrated circuits will impose a new set of criteria upon network synthesis.
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