{"title":"用于多级模数转换的管道级的设计和分析","authors":"G. Deliyannides, H. Kwok","doi":"10.1109/CCECE.1997.614811","DOIUrl":null,"url":null,"abstract":"An architecture is proposed to achieve high speed analog-to-digital conversion. This architecture is based on the multi-stage analog-to-digital conversion technique. The multistage method utilizes pipelining to allow concurrent operation of smaller conversion segments. These segments are appended to form a composite result. Through pipelining, a reduction in circuit area is also achieved.","PeriodicalId":359446,"journal":{"name":"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings","volume":"84 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"The design and analysis of a pipeline stage for use in a multistage analog-to-digital conversion\",\"authors\":\"G. Deliyannides, H. Kwok\",\"doi\":\"10.1109/CCECE.1997.614811\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An architecture is proposed to achieve high speed analog-to-digital conversion. This architecture is based on the multi-stage analog-to-digital conversion technique. The multistage method utilizes pipelining to allow concurrent operation of smaller conversion segments. These segments are appended to form a composite result. Through pipelining, a reduction in circuit area is also achieved.\",\"PeriodicalId\":359446,\"journal\":{\"name\":\"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings\",\"volume\":\"84 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-05-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CCECE.1997.614811\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CCECE.1997.614811","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The design and analysis of a pipeline stage for use in a multistage analog-to-digital conversion
An architecture is proposed to achieve high speed analog-to-digital conversion. This architecture is based on the multi-stage analog-to-digital conversion technique. The multistage method utilizes pipelining to allow concurrent operation of smaller conversion segments. These segments are appended to form a composite result. Through pipelining, a reduction in circuit area is also achieved.