晶圆级芯片规模封装的参数化焊点可靠性模型

J. Pitarresi, S. Chaparala, B. Sammakia, L. Nguyen, V. Patwardhan, L. Zhang, N. Kelkar
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引用次数: 11

摘要

micro-SMD是一种晶圆级芯片级封装(WL-CSP),其外部尺寸与硅器件相同。这种新的封装类型将倒装芯片封装技术扩展到标准表面贴装技术。该封装已成功瞄准低引脚数(小于30),大容量应用,如蜂窝电话,手持pda等。由于WL-CSP通常不使用下填料,因此焊点可靠性是首要考虑的问题。当组装在不同的电路板配置上时,对器件失效机制的良好理解对于开发准确的焊料疲劳预测模型至关重要。本文介绍了在热机械应力作用下微型smd焊点可靠性的参数预测模型的共同努力的结果。一个18 I/O微型smd被用作主要的测试工具,在不同的斜坡/保持剖面下进行热循环和热冲击测试。所建立的参数化模型可扩展到不同引脚数和共晶焊料w - csp的模具尺寸。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A parametric solder joint reliability model for wafer level-chip scale package
The micro-SMD is a Wafer Level-Chip-Scale Package (WL-CSP) designed to have external dimensions equal to that of the silicon device. This new package type extends flip-chip packaging technology to standard surface mount technology. The package has been successfully targeted for low pin count (less than 30), high volume applications such as cellular phones, hand-held PDAs, etc. Since the WL-CSP is typically used without underfill, solder joint reliability is of prime concern. A good understanding of the device failure mechanism when assembled on different board configurations is critical to the development of an accurate predictive model of solder fatigue. This paper presents results of a joint effort to develop a parametric predictive model of the solder joint reliability of the micro-SMD subjected to thermo-mechanical stresses. An 18 I/O micro-SMD was used as the primary test vehicle for the thermal cycling and thermal shock tests performed with different ramp/hold profiles. The parametric model developed can be extended to different pin count and die size of WL-CSPs with eutectic solder.
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