Design and Analysis of 8-bit Vedic Multiplier

Multipliers are utilized in a wide range of DSP applications nowadays, including vector product, filtering, convolution operations, matrix multiplication, etc. The parameters which are important to consider with precision are speed of operation, chip space occupied, ease of design, power consumption, high noise immunity, and so on. In this paper comparison of the maximum combinational path latency, chip area consumption, and total on-chip power of an 8-bit Vedic multiplier using Urdhva Tiryagbhyam method, an 8-bit Wallace tree multiplier, and 8bit Array Multiplier written in Verilog has been done. For proper comparison, all multipliers are made with full adders, half adders, n-bit adders, and basic gates. Creation and the simulation of the stated multipliers using Xilinx ISE 14.7 on device 6slx9tqg144-2 and implementation of the 8-bit Vedic multiplier on EDGE Spartan 7 FPGA Board has been done to validate the same. Design of Vedic multiplier and it’s comparison with above mentioned multipliers is presented in this paper.