采用0.12 /spl mu/m STI工艺技术的1.8 V 1gb NAND闪存

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.992121

J. Lee, Heung-Soo Im, D. Byeon, Kyeong-Han Lee, Dong-Hyuk Chae, Kyongjoo Lee, Y. Lim, Jungdal Choi, Young-Il Seo, Jong-Sik Lee, K. Suh

{"title":"采用0.12 /spl mu/m STI工艺技术的1.8 V 1gb NAND闪存","authors":"J. Lee, Heung-Soo Im, D. Byeon, Kyeong-Han Lee, Dong-Hyuk Chae, Kyongjoo Lee, Y. Lim, Jungdal Choi, Young-Il Seo, Jong-Sik Lee, K. Suh","doi":"10.1109/ISSCC.2002.992121","DOIUrl":null,"url":null,"abstract":"A 1.8 V 1 Gb flash memory uses a 0.12 /spl mu/m STI process technology. A charge pump operates at <1.8 V. A center-placed row decoder is digitized in one block pitch by applying a 32-cell NAND structure. A page buffer, containing two latches, supports a cache-program to improve program speed to 7 MB/s.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A 1.8 V 1 Gb NAND flash memory with 0.12 /spl mu/m STI process technology\",\"authors\":\"J. Lee, Heung-Soo Im, D. Byeon, Kyeong-Han Lee, Dong-Hyuk Chae, Kyongjoo Lee, Y. Lim, Jungdal Choi, Young-Il Seo, Jong-Sik Lee, K. Suh\",\"doi\":\"10.1109/ISSCC.2002.992121\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 1.8 V 1 Gb flash memory uses a 0.12 /spl mu/m STI process technology. A charge pump operates at <1.8 V. A center-placed row decoder is digitized in one block pitch by applying a 32-cell NAND structure. A page buffer, containing two latches, supports a cache-program to improve program speed to 7 MB/s.\",\"PeriodicalId\":423674,\"journal\":{\"name\":\"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)\",\"volume\":\"76 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2002.992121\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2002.992121","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

1.8 V 1gb闪存采用0.12 /spl mu/m STI工艺技术。电荷泵工作在<1.8 V。通过应用32单元NAND结构，在一个块间距内数字化放置在中心的行解码器。包含两个锁存器的页缓冲区支持一个缓存程序，可将程序速度提高到7 MB/s。

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A 1.8 V 1 Gb NAND flash memory with 0.12 /spl mu/m STI process technology

A 1.8 V 1 Gb flash memory uses a 0.12 /spl mu/m STI process technology. A charge pump operates at <1.8 V. A center-placed row decoder is digitized in one block pitch by applying a 32-cell NAND structure. A page buffer, containing two latches, supports a cache-program to improve program speed to 7 MB/s.

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2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

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